“The VLSI Packaging Workshop in Japan” held every other year since 1992 has become a well-known international workshop for advanced packaging technologies. Due to ever increasing activities and changing demands, the committee has reviewed its mission, cooperated with the members of IEEE CPMT Japan Chapter, refurbished the workshop, and started the new symposium - IEEE CPMT Symposium Japan. It will provide component, packaging, and manufacturing researchers who are extending their activities beyond borders with opportunities to exchange technical knowledge and perspective. The committee strongly encourages you to attend this symposium and participate in the discussion, to understand the technology trends and find the best targets for your technology / business development. Bring your latest research results and share with the participants who are experts from the industry and the grove of Academe, and discuss with them. Anybody contributing to the achievement of a sustainable society through electronics is very welcome at this symposium.

◆ 3D Packaging & Chip on Chip

◆ Advanced Fine Pitch Packaging

◆ Assembly and Packaging Challenges for Cu/Low-k Chips

◆ Borad level reliability System in a Package (SiP)

◆ Electrical Performance & Thermal Management

◆ Emerging Technologies

◆ Failure Mechanisms & Reliability Improvement

◆ Green Material

◆ Integrated Passives / Embedded Components

◆ Laminated Materials & Processing

◆ Materials for High Speed Application & Wafer Process

◆ MEMS Packaging

◆ Micro Bumping Technology

◆ Nano-Technology

◆ Packaging for Automobile

◆ Packaging for Optoelectronics

◆ RF Components & Modules / RF Tags

◆ System in a Package (SiP)

◆ Wafer Level CSP

You are invited to submit a 500-word abstract to the program chair with the reference of maximum two diagrams.
Acceptance will be notified by Mar. 31st.
Abstract due: Feb 15th, 2010

Submit to: Program Chair:
　　Dr. Shigenori Aoki
　　E-mail: aoki.shigenori@jp.fujitsu.com
　　URL: http://vlsi-pkg-ws.org/

Program Chair: 　Dr. Shigenori Aoki 　Fujitsu Laboratories Ltd. 　10-1 Morinosato-Wakamiya, 　Atsugi, Kanagawa 243-0197, 　JAPAN 　Phone: +81-46-250-8183 　Fax: +81-46-248-6000 　E-mail: aoki.shigenori@jp.fujitsu.com

General Chair: 　Dr. Tadatomo Suga, 　The University of Tokyo Executive chair: 　Dr. Hirofumi Nakajima, 　NEC Electronics Corporation Vice Chair: 　Dr. Hiroshi Yamada, 　Toshiba Corporation 　 Dr. Ricky Lee, 　HKUST, Hong Kong

IEEE CPMT Japan Chapter Chair: 　Dr. Masahiro Aoyagi, 　Advanced industrial science and　technology Vice Chair: 　Dr. Kishio Yokouchi, 　Fujitsu Interconnect Technologies Ltd.

---

Japanese Committee:	US Committee:
Noriko Fujita, Sanyu Rec Co., Ltd. Michitaka Kimura, Renesas Technology Corp. Kaoru Kobayashi, Kyocera SLC Technologies Corporation Hiroshi Manita, Casio Computer Co., Ltd. Atsushi Nakamura, Renesas Technology Corp. Tomoshi Ohde, Sony Corporation Atsushi Okuno, Sanyu Rec Co., Ltd. Kanji Otsuka, Meisei University Toshio Sudo, Shibaura Institute of Technology	William Chen, Advanced Semiconductor Engineering Phillip Garrou, Microelectronics Consultants of North Carolina Keith Newman, Sun Microsystems Ephraim Suhir, University of California E. Jan Vardaman, TechSearch International, INC. C. P. Wong, Georgia Institute of Technology Jie Xue, Cisco Systems, Inc.
	European Committee:
	Rolf Aschenbrenner, Fraunhofer-IZM, Germany Chria Bailey, University of Greenwich, United Kingdom Eric Beyne, Interuniversity Microelectronics Center, Belgium Klaus Pressel, Infineon Technologies AG., Germany
IEEE CPMT Japan Chapter
Yasuhiro Ando, Fujikura Ltd. Masazumi Amagai, Texas Instruments Japan Ltd. Yoshitaka Fukuoka, WEISTI Kaoru Hashimoto, Meisei University Hideyuki Ohashi, Mitsubishi Electric Co.
	Asian Committee:
	Kuo-Ning Chiang, ITRI & National Tsing Hua University, Taiwan C. P. Hung, Advanced Semiconductor Engineering, Taiwan Seok-Hwan Huh, Samsung Electronics Co. Ltd., Korea Joungho Kim, Korea Advanced Institute of Science and Technology, Korea John H. Lau, Institute of Microelectronics, Singapore

Last updated:  2009/12/24