IEEE 9th VLSI Packaging Workshop in Japan
(VPWJ2008)
Dec. 1 - 2, 2008
The Westin Miyako, Kyoto, Japan
It is the date for workshop soon
We wait for the participation of a lot of engineers
Please register right now!
Ginkaku-Ji (Jisho-ji) Photed by Mr. Katayama
Sponsored by The IEEE CPMT Society and
NIST
Technical Topics of this Workshop
| ◆System in a Package (SiP) | ◆MEMS Packaging Technologies |
| ◆Advanced Fine Pitch Packaging | ◆Nano-Technology |
| ◆Wafer Level CSP | ◆Micro Bumping Technology |
| ◆Packaging for Optoelectronics | ◆Electrical Performance & Thermal Managemen |
| ◆Packaging for Automobile | ◆Failure Mechanisms & Reliability Improvement |
| ◆RF Components & Modules / RF Tags | ◆Materials for High Speed Application & Wafer Process |
| ◆Integrated Passives / Embedded Components | ◆ Green Material |
| ◆Laminated Materials & Processing | ◆Assembly and Packaging Challenges for Cu/Low-k Chips |
| ◆Emerging Technologies |
Last updated: 2008/9/15
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