IEEE CPMT Symposium Japan,
formerly VLSI Package Workshop in Japan
Aug.24 - 26, 2010

The University of Tokyo, Hongo Campus
Faculty of Engineering Bldg.2
Sanjo Conference Hall

 

The University of Tokyo, Yasuda Auditorium

Register now to benefit from reduced registration fees!

Technical Topics of this Workshop

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System in a Package (SiP)

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MEMS Packaging Technologies

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Advanced Fine Pitch Packaging

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Nanotechnology

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3D Packaging & COC (Chip on Chip)           

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Micro Bumping Technology

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Wafer Level CSP

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Electrical Performance & Thermal Management

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Packaging for Optoelectronics

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Failure Mechanisms & Reliability Improvement

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Packaging for Automobile

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Materials for High Speed Application &
Wafer Process

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RF Components & Modules / RF Tags

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Green Material

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Assembly and Packaging Challenges for
Cu/Low-k Chips

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Integrated Passives /Embedded Components

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Laminated Materials & Processing

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Emerging Technologies

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Board level reliability System in a Package (SiP)

 
 Last updated:  2010/ 7/10
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